1. Technical Field
This invention relates to new and useful improvements in data processing systems. More specifically, it relates to an apparatus for extending a bus architecture to allow many individual workstation or PC systems to perform high-speed communications in parallel while maintaining bus addresses constant and making the expansion transparent to software.
2. Description of the Prior Art
The problem exists in PC's and workstations that there is an ever increasing need for better I/O bus performance and the attachment of more I/O options. This is in direct conflict with the nature of a multi-drop bus technology, which loses performance as more I/O options are added as taps to the bus. In general, standard bus architectures such as the microchannel bus (MC) have selected a performance goal and have backward engineered the number of I/O taps permissible at that performance level. In the case of the microchannel bus the result is that 8 taps (expansion cards) is the maximum number of allowable bus taps to permit bus operations to occur at 200 ns cycle times. As a result MC users are beginning to find that the I/O capability is not sufficient to meet their needs. For years people having been looking for means of increasing the I/O capability of PC busses, and still require a good solution.
Some machines have been packaged with separate microchannel buses in one cabinet to increase the number of expansion cards in one system. The disclosed solution is much more flexible in that it allows unlimited expansion. Also, the disclosed solution permits any tap to transfer data to any other tap, while the previous systems allow only limited combinations.
U.S. Pat. No. 5,088,028 discloses an bus-to-bus interface circuit for communicating data between two computer systems. The interface circuit permits the first bus (VMEbus) to gain control of the second bus (Futurebus) to prevent another bus from gaining access to it.
U.S. Pat. No. 5,083,259 discloses an interconnection device For attaching an AT computer to a VMEbus and allowing the AT computer to access the bus in real mode.
U.S. Pat. No. 5,006,981 discloses a system for coupling multimaster capable buses. The system includes an expansion module for each bus for receiving and sending addresses, data, commands and status signals.
U.S. Pat. No. 5,123,092 discloses a bus interface for connecting a computer's internal bus to an expansion bus. The interface is capable of selecting or deselecting any other device connected to the expansion bus.
U.S. Pat. No. 5,138,703 discloses a method and apparatus for expanding a system bus, providing a capability of transferring a data word from a unit connected to a system bus to a unit connected to an extension bus.